Selected Publications

Many of the publications listed below are copyrighted by IEEE or ACM. LCA owns copyrights of all unpublished manuscripts listed below. Personal use of these materials is permitted. However, permission to reprint or replublish these materials for resale or redistribution purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works,must be obtained from the IEEE/ACM/LCA.
Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon? [PDF]
Reena Panda*, Shuang Song*, Joseph Dean, and Lizy K. John (Reena and Shuang are both co-first authors).
IEEE International Symposium on High-Performance Computer Architecture(HPCA). February 2018.
CSALT: Context Switch Aware Large TLB [PDF]
Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, and Lizy K. John.
International Symposium on Microarchitecture (MICRO). October 2017.
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB [PDF]
Jee Ho Ryoo, Nagendra Gulur, Shuang Song, and Lizy K. John.
International Symposium on Computer Architecture (ISCA). June 2017.
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization [PDF]
Jee Ho Ryoo, Mitesh R. Meswani, and Lizy K. John.
The IEEE Symposium on High Performance Computer Architecture (HPCA). February 2017.
AUDIT: Stress Testing the Automatic Way [PDF]
Youngtaek Kim, Sanjay Pant, Srilatha Manne, Michael Schulte, Lloyd Bircher, Madhu Saravana Sibi Govindan, and Lizy K. John.
The 45th International Symposium on Microarchitecture (MICRO'45). December 2012.
A First-Order Mechanistic Model for Architectural Vulnerability Factor [PDF]
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, and Lizy K. John.
The 39th Interenational Symposium on Computer Architecture (ISCA-39). June 2012.
Modeling Program Resource Demand Using Inherent Program Characteristics [PDF]
Jian Chen, Lizy K. John, and Dimitris Kaseridis.
International Symposium on Measurement and Modeling of Computer System (SIGMETRICS) . June 2011.
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
Jeffery Stuecheli, Dimitris Kaseridis, Lizy K. John, David Daly, and Hillery C. Hunter.
IEEE Micro. Vol. 31. No. 1. pp 90-98. January 2011.
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-case Vulnerability to Soft Errors [PDF]
Arun A. Nair, Lizy K. John, and Lieven Eeckhout.
The 43rd Interenational Symposium on Microchitecture. December 2010.
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory [PDF]
Jeff Stuecheli, Dimitris Kaseridis, David Daly, Hillery Hunter, and Lizy K. John.
The 43rd Interenational Symposium on Microchitecture. December 2010.
The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies [PDF]
Jeff Stuecheli, Dimitris Kaseridis, David Daly, Hillery Hunter, and Lizy K. John.
The 37th Interenational Symposium on Computer Architecture. June 2010.
Bandwidth-aware Memory-subsystem Resource Management using Non-invasive Resource Profilers for Large CMP Systems [PDF]
Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, and Lizy K. John.
The 16th International Symposium on High-performance Computer Architecture . January 2010.
Value Based BTB Indexing (VBBI) for Indirect Jump Prediction (Best Paper Nominee) [PDF]
Muhammad Umar Farooq, Lei Chen, and Lizy K. John.
The 16th Interenational Symposium on High-Performance Computer Architecture. January 2010.
ESKIMO - Energy Savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem [PDF]
Ciji Isen and Lizy K. John.
The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December 2009.
Automated Microprocessor Stressmark Generation [PDF]
Ajay Joshi, Lieven Eeckhout, Lizy K. John, and Ciji Isen.
The 14th International Symposium on High Performance Computer Architecture (HPCA) . February 2008.
Analysis of Redundency and Application Balance in the SPEC CPU2006 Benchmark Suite [PDF]
Aashish Phansalkar, Ajay Joshi, and Lizy K. John.
The 34th International Symposium on Computer Architecture (ISCA) . June 2007.
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies [PDF]
Lieven Eeckhout, Robert H. Bell, Jr., Bastiaan Stougie, Koen De Bosschere, and Lizy K. John.
International Symposium on Computer Architecture (ISCA). pp 350-361. June 2004.
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors [PDF]
Ravi Bhargava and Lizy K. John.
30th International Symposium on Computer Architecture (ISCA'03). pp 264-274. June 2003.
Run-time Modeling and Estimation of Operating System Power Consumption [PDF]
Tao Li and Lizy John.
International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS). pp 160-171. June 2003.
Understanding and Improving Operating System Effects in Control Flow Prediction [PDF]
Tao Li, Lizy John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, and Juan Rubio.
10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X). pp 68-80. October 2002.
Allowing for ILP in an Embedded Java Processor [PDF]
Ramesh Radhakrishnan, Deepu Talla, and Lizy John.
International Symposium on Computer Architecture. pp 294-305. June 2000.
Architectural Issues in Java Runtime Systems [PDF]
Ramesh Radhakrishnan, N. Vijaykrishnan, Lizy John, and Anand Sivasubramaniam.
International Symposium on High Performance Computer Architecture. pp 387-398. January 2000.
Evaluating MMX Technology Using DSP and Multimedia Applications [PDF]
Ravi Bhargava, Lizy John, Brian L. Evans, and Ramesh Radhakrishnan.
IEEE Symposium on Microarchitecture. pp 37-46. December 1998.
Program Balance and Its Impact on High Performance RISC Architectures [PS] [PDF]
Lizy Kurian, Vinod Reddy, Paul Hulina, and Lee Coraor.
International Symposium on High Performance Computer Architecture. pp 370-379. January 1995.
Memory Latency Effects in Decoupled Architectures with a Single Memory Module [PS]
Lizy Kurian, Paul T. Hulina, and Lee D. Coraor.
19th International Symposium On Computer Architecture. pp 236-245. May 1992.
Classification and Performance Evaluation of Instruction Buffering Techniques [PDF]
Lizy Kurian, Paul T. Hulina, Lee D. Coraor, and Dhamir N. Mannai.
18th International Symposium on Computer Architecture. pp 150-159. May 1991.