Refereed Publications

   Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design
   Multicore Processors

   Karthik Ganesan and Lizy K John
   In the IEEE Transactions on Computers, 2013

   Automatic Generation of Synthetic Workloads for Multicore Systems
   Karthik Ganesan
   Department of Electrical and Computer Engineering, The University of Texas at Austin, Dec 2011. Hororable
   mention for the 2012 SPEC Distinguished Dissertation Award

   MAximum Multicore POwer (MAMPO) - An Automatic Multithreaded Synthetic Power Virus
   Generation Framework for Multicore Systems

   Karthik Ganesan and Lizy K. John.
   Best paper finalist in the SuperComputing Conference (SC 2011), Seattle, WA, Nov 2011
   and is also selected for presentation at TECHCON 2011, Austin, TX, Sep 2011

   System-level Max Power (SYMPO) - A systematic approach for escalating system-level power
   consumption using synthetic benchmarks

   Karthik Ganesan, Jungho Jo, W. Lloyd Bircher, Dimitris Kaseridis, Zhibin Yu and Lizy K. John.
   In the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT),
   Vienna, Austria, September 2010

   Synthesizing Memory-Level Parallelism Aware Miniature Clones for SPEC CPU2006 and    ImplantBench Workloads
   Karthik Ganesan, Jungho Jo and Lizy K. John
   In 2010 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),
   White Plains, NY, March 2010

   A Performance Counter Based Workload Characterization on BlueGene/P
   Karthik Ganesan, Lizy K. John, James Sexton, and Valentina Salapura
   In 37th International Conference on Parallel Processing (ICPP), Portland, Oregon, September 2008

   Next-Generation Performance Counters: Monitoring Over Thousand Concurrent Events
   Valentina Salapura, Karthik Ganesan, Alan Gara, Michael Gschwind, James C. Sexton, and Robert E. Walkup
   In 2008 International Symposium on Performance Analysis of Systems and Software (ISPASS),
   Austin, Texas, April 2008

   Future Generation Supercomputers II: A Paradigm for Cluster Architecture
   N. Venkateswaran, D. Srinivasan, M. Manivannan, T. P. Sagar, S. Gopalakrishnan, V. K. Elangovan, M. Arvind,
   P. K. Ramesh, Karthik Ganesan, V. Krishnamurthy, Sivaramakrishnan
   ACM SIGARCH Computer Architecture News Volume 35, Issue 5 Dec 2007, Pages 61-70

   On the Concept of Simultaneous Execution of Multiple Applications on Hierarchically Based
   Cluster and the Silicon Operating System

   N. Venkateswaran, V. K. Elangovan, Karthik Ganesan, S. Aananthakrishanan, S. Ramalingam, S. Gopalakrishnan,
   M. Manivannan, D. Srinivasan, V. Krishnamurthy, K. Chandrasekar, V. Venkatesan, B. Subramaniam, V. Sangkar,
   A. Vasudevan, S. Ganapathy, S. Murali, M. Thyagarajan
   In IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008, Miami, Florida, USA.

   Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch,
    Memory, and TLB Characteristics

   Karthik Ganesan, Deepak Panwar, and Lizy John
   In 2009 SPEC Benchmark Workshop, Austin, Texas, January 2009.

   Workload Synthesis for a Communications SoC
   Lizy John, Jungho Jo and Karthik Ganesan
   In Workshop on SoC Architecture, Accelerators and Workloads, held in conjunction with HPCA-17, San Antonio,
   Texas, Feb 2011.

   Simulation Model for predicting the Multi-Million Neuron Interconnectivity involving
   Dendrites-Axon-Soma-Synapse of the Brain Regions whose BOLD-fMRI is known and Evolution
   of a neurophysiologically Inspired Supercomputing Architecture for Modeling the Respective
   Brain Regions.

   Venkateswaran Nagarajan, Karthik Ganesan et. al
   In International Workshop on Data driven Modeling and Computation in Neuroscience,
   Heidelberg, Germany, May 18-21, 2005 conducted by the Nobel laurete Bert Sakmann.

   High Performance Low Power Single Chip Reconfigurable Supercomputer for
   High-end Aerospace Applications

   Venkateswaran N, Arvind M, Karthik C, Karthik Ganesan, Vishwanath V and Viswanath K
   In 2005 MAPLD International conference on Military & Aerospace Programmable Logic Devices conducted by NASA
   Washington D.C., September 7-9, 2005

   Hierarchical Multihost Based Operating System For Simultaneous Multiple Application Execution
   on MIP SCOC Cluster

   Karthik Ganesan
   Dissertation, WAran Research FoundaTion (WARFT), 2006

   Memory Efficient Application Execution In MIP SCOC
   Venkateswaran Nagarajan, Karthik Ganesan et. al
   In WARFT Workshop on Brain modeling and Supercomputing, Chennai, India, March 27-30, 2006 conducted by
   Waran Research Foundation.

   Emulating IBM BlueGene on a Linux MPI Cluster
   Karthik Ganesan and Vishwanath Venkatesan
   Dissertation (best project award), Anna University, 2006.