Research Topics

• Computer Architecture
• Performance Evaluation
• Circuit Design & VLSI Testing

Refereed publications per category

• Computer Architecture

  • "Cache Friendliness-Aware Management of Last-level Caches for High Performance Multi-core Systems," accepted in IEEE Transactions on Computers, January 2013 [Pre-print Link]
  • "Minimalist Open-page: A DRAM Page-mode Scheduling Policy for the Many-core Era," the 44^th International Symposium on Microarchitecture (MICRO), Dec. 2011 (Nominated for best paper award) [PDF]
  • "MCFP: A Memory-level Parallelism and Applications' Cache Friendliness Aware Pseudo-Partitioning Scheme for Last-level Shared Caches," the 20^th International Conference on Parallel Architectures and Compilation Techniques, Poster Session (PACT), Oct. 2011
  • "Modeling Program Resource Demand Using Inherent Program Characteristics," the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), June 2011 [PDF]
  • "Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue," the IEEE Micro Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences, IEEE Micro, vol. 31, no. 1, (MICRO TOP-PICKS) Jan./Feb. 2011 (One of the computer architecture papers of 2010 selected as Top Picks by IEEE Micro)
  • "Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory," the 43^rd International Symposium on Microarchitecture (MICRO), Dec. 2010 [PDF] [PPT]
  • "System-level Max Power (SYMPO) - A systematic approach for escalating system-level power consumption using synthetic benchmarks," the 19^th International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2010 [PDF] [PPT]
  • "The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies," the International Symposium on Computer Architecture (ISCA), June 2010 [PDF] [PPT]
  • "A Bandwidth-aware Memory-subsystem Resource Management using Non-invasive Resource Profilers for Large CMP Systems," the 16^th International Symposium on High Performance Computer Architecture (HPCA), Jan. 2010 [PDF] [PPT]
  • "Bank-aware Dynamic Cache Partitioning for Multicore Architectures," the 38^th International Conference on Parallel Processing (ICPP), Sept. 2009. (Won best Paper Award) [PDF] [PPT]

• Performance Evaluation

  • "A Machine Learning Based Search Approach to Synthesize System-level Power Viruses," the Technology and Talent for the 21st Century (TECHCON), Austin, Sept. 2010
  • "CMP/CMT Scaling of SPECjbb2005 on UltraSPARC T1," the 10th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-10), Feb. 2007 [PDF] [PPT]
  • "Performance Analysis of Multiple Threads/Cores Using the UltraSPARC T1," Workshop on Unique Chips and Systems (UCAS-4), 2008 [PDF] [PPT]

• Circuit Design & VLSI Testing

  • "Reseeding-based Test Set Embedding with Reduced Test Sequences," the International Symposium on Quality Electronic Design (ISQED), 2005 (One of the four papers nominated for best paper award) [PDF] [PPT]
  • "An Efficient Test Set Embedding Scheme with Reduced Test Data Storage and Test Sequence Length Requirements for Scan-based Testing," the European Test Symposium (ETS), 2005 (Informal Digest) [PDF] [Poster]

Disclaimer

Many of the publications listed above are copyrighted by IEEE or ACM. Dimitris Kaseridis owns copyrights of all unpublished manuscripts listed above. Personal use of these materials is permitted. However, permission to reprint or replublish these materials for resale or redistribution purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE/ACM and Dimitris Kaseridis, respectively.