Research Topics

Microprocessor Architecture

Our work currently focus on the challenges that computer architects will face in the future. We are investigating techniques to efficiently utilize the 100 million or billion transistors on a chip that manufacturing technologies will provide in the coming years. We are analyzing tradeoffs in single chip multiprocessors, wide superscalars, and simultaneous multithreaded architectures. The analysis uses SimOS and SuperSim, our in-house superscalar processor simulator.

Also, as the gap increases between the speed of processors and the speed of memory, it is necessary to come up with new ways to organize the data. We are currently looking at different memory configurations, hierarchies and data partitioning algorithms that can minimize the number of off-chip (or off-node) memory accesses and/or minimize the latencies observed by the processing unit. We are also investigating new structures to make the memory hierarchy efficient.

One important ongoing research project is the Code Coalescing Unit (CCU), which promises to dynamically reduce the number of memory accesses, eliminating the accesses that resulted from register spills.

Performance Impact of Contemporary Programming Paradigms

In this project, we explore techniques to match processor architectures to modern software development practices and applications including Object Oriented Programming, Data Minning and Network Computing. It is likely that cache design, branch prediction, instruction scheduling techniques and several other processor designs aspects have to be reconsidered when migrating to modern workloads.

The expected outcome of this research is a through understanding of how processor design can be better matched to modern software development practices.

Currently we are analyzing the effects that Object Oriented Programming (OOP) has on the execution of an application. Our initial research utilizes C++ and Java as they account for high percentages of all the currently available OOP applications.

Also interesting is the client-server programming paradigm. Under this scheme, the performance of the system does not only depend on the performance of the individual sub-systems, but also on the communication between them. We are doing research on the Java-CORBA architecture in order to determine how system efficiency and performance is getting affected by the newer programming paradigms.

Workload Characterization

We strongly believe in the need of better mechanisms to characterize applications. Understanding the nature of programs and the workload behavior leads to the design of improved architectures.

Currently we are investigating methodologies to characterize applications at an abstract level, which allow us to identify the generic properties of the application in terms of its memory access behavior, locality, branch behavior, instruction level parallelism, etc. The proposed effort is to identify abstract metrics of program behavior and correlate them with observed quantitative metrics, and create a machine-independent program behavior models.

Simultaneously we are developing benchmarks beyond SPEC95 and which we believe reflect different sets of emerging workloads. We are currently working on client-server benchmarks using the web as the communication channel and also Java-CORBA.

High Performance Digital Signal Processing

It is a fact that multimedia applications account for a considerable and growing percentage of today's workloads. This has been noticed by microprocessors designers as it is evident from the introduction of the Single Instruction Multiple Data (SIMD) extensions virtually all modern general purpose processors.

The execution of multimedia applications has other implications over the way traditional general-purpose computer systems are designed. Most of them related with a resulting unbalance of the system, which results into memory bound applications and computation bound applications. Our research tries to identify mechanisms to improve the balance between memory access and true computations in order to exploit high concurrency and achieve high performance. An essential part of our research is a detailed evaluation of Decoupled DSP processors, comparing them with other advanced architectural techniques such as superscalar and VLIW execution.

Compiler Support for Innovative Microarchitectures

As computer architectures and compilers evolve, the need for a more consistent interaction between the two becomes more apparent. It is no longer reasonable to accept the idea of a compiler totally detached from the architectural details, which until now were hidden by a well defined and stable Instruction Set Architecture (ISA). Likewise microarchitecture designers have to be aware of the different programming and data access patterns and not just the flow of raw instructions.

Our research focus primarily on identifying mechanism that will allow compilers to provide hints to the microarchitecture in order to increase its efficiency and maximize the performance. We are currently looking at the tradeoffs of data prefetching and bus utilization, as well as compiler support for innovative mechanisms such as the Code Coalescing Unit (CCU).