Texas Advanced Technology Program

We propose a comprehensive research program to investigate techniques to improve the parallelism and concurrency in high performance digital signal processors (DSP). The primary focus will be on the memory accessing capability of DSP architectures and the parallelism between the access operations and the actual computations. We will devise architectural techniques to exploit program parallelism and improve performance with minimal overhead.

Most DSP algorithms involve a lot of number crunching and in most cases, there are more access operations to be performed than actual computations. However, the functional unit mix in most general purpose processors and DSPs is typically in favor of efficient computing rather than efficient memory accessing. Unless the access process can be done efficiently, and in parallel, the computation units cannot be utilized to their full capacity. The proposed project will specifically address the memory access bottleneck and investigate solutions to improve the access capability of DSPs.

This research effort will investigate issues in the design of a digital signal processor architecture that improves the balance between the memory access and true computations performed by the applications, maximizes the decoupling between the various functional units, exploits high concurrency and achieves high performance. The performance of a decoupled DSP processor will be evaluated in comparison to other advanced architectural techniques such as superscalar and VLIW execution.

Dynamic multimedia component technologies such as video-conferencing, video authoring, 3D graphics, animation, speech recognition and broadband communications have become a dominant fraction of the workload on desktop machines. We propose a research project to design and develop the architecture for a processor that is tailored towards executing this class of emerging applications. Lack of quantitative information on multi-media workloads has been a problem to microprocessor designers while attempting to architect signal processing extensions such as the Intel MMX or AMD 3DNow!, or DSP chips such as Texas Instruments C62xx processor. We propose to perform detailed workload characterization to obtain a thorough understanding of emerging multimedia applications. Second, based on the understanding derived from our recent and ongoing workload characterization, we propose to develop architectural innovations to cater to the special needs of media applications.